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GS82582QT20GE-400I

Name: GSI Technology GS82582QT20GE-400I
Brand: GSI Technology
SKU: 464-82582QT20GE400I
Price: 8010699 IDR
Availability: OutOfStock

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Mouser No:

464-82582QT20GE400I

Mfr. No:

GS82582QT20GE-400I

Mfr.:

GSI Technology

Description:

SRAM 1.5/1.8V 16M x 18 288M

Datasheet:

GS82582QT20GE-400I Datasheet (PDF)

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Learn more about GSI Technology GS82582QT20GE-400I

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Pricing (IDR)

Qty.	Unit Price	Ext. Price
	Rp8.010.699	Rp80.106.990

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	GSI Technology
Product Category:	SRAM
RoHS:
Memory Size:	288 Mbit
Organisation:	16 M x 18
Maximum Clock Frequency:	400 MHz
Interface Type:	Parallel
Supply Voltage - Max:	1.9 V
Supply Voltage - Min:	1.7 V
Supply Current - Max:	1.18 A
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 85 C
Mounting Style:	SMD/SMT
Package/Case:	BGA-165
Packaging:	Tray
Brand:	GSI Technology
Country of Assembly:	Not Available
Country of Diffusion:	Not Available
Country of Origin:	Not Available
Memory Type:	QDR-II
Moisture Sensitive:	Yes
Product Type:	SRAM
Series:	GS82582QT20GE
Factory Pack Quantity:	10
Subcategory:	Memory & Data Storage
Tradename:	SigmaQuad-II+
Type:	SigmaQuad-II+ B2

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Datasheet

GS82582QT20GE-400I Datasheet (PDF)

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CNHTS:: 8542319090
CAHTS:: 8542320041
USHTS:: 8542320041
JPHTS:: 854232029
KRHTS:: 8542321020
TARIC:: 8542324500
MXHTS:: 8542320201
ECCN:: 3A991.b.2.b

SigmaQuad-II+ SRAMs

GSI Technology SigmaQuad-II+ SRAMs have built-in compliance with the SigmaQuad-II+ SRAM pinout standard for Separate I/O synchronous SRAMs. The SigmaQuad-II+ are 301,989,888-bit (288Mb) SRAMs. The SigmaQuad-II+ SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.

Quad SRAMs

GSI Technology Quad SRAMs combine capacity and performance with the ability to transfer four beats of data (two beats per data bus) in a single clock cycle. SigmaQuad SRAMs are synchronous memories with separate read and write data buses with unequaled transaction rates by competitors.