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GS8662QT07BGD-357

Name: GSI Technology GS8662QT07BGD-357
Brand: GSI Technology
SKU: 464-GS8662QT07BGD357
Price: 3327354 IDR
Availability: OutOfStock

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Mouser No:

464-GS8662QT07BGD357

Mfr. No:

GS8662QT07BGD-357

Mfr.:

GSI Technology

Description:

SRAM 1.8 or 1.5V 8M x 8 64M

Datasheet:

GS8662QT07BGD-357 Datasheet (PDF)

ECAD Model:

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Pricing (IDR)

Qty.	Unit Price	Ext. Price
	Rp3.327.354	Rp49.910.310
	Rp3.216.647	Rp96.499.410
	Rp3.124.858	Rp187.491.480
105	Quote

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	GSI Technology
Product Category:	SRAM
RoHS:
Memory Size:	72 Mbit
Organisation:	8 M x 8
Maximum Clock Frequency:	357 MHz
Interface Type:	Parallel
Supply Voltage - Max:	1.9 V
Supply Voltage - Min:	1.7 V
Supply Current - Max:	985 mA
Minimum Operating Temperature:	0 C
Maximum Operating Temperature:	+ 70 C
Mounting Style:	SMD/SMT
Package/Case:	BGA-165
Packaging:	Tray
Brand:	GSI Technology
Country of Assembly:	Not Available
Country of Diffusion:	Not Available
Country of Origin:	Not Available
Memory Type:	DDR
Moisture Sensitive:	Yes
Product Type:	SRAM
Series:	GS8662QT07BGD
Factory Pack Quantity:	15
Subcategory:	Memory & Data Storage
Tradename:	SigmaQuad-II+
Type:	SigmaQuad-II+ B2

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Datasheet

GS8662QT07BGD-357 Datasheet (PDF)

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CNHTS:: 8542319090
CAHTS:: 8542320041
USHTS:: 8542320041
JPHTS:: 854232029
KRHTS:: 8542321020
TARIC:: 8542324500
MXHTS:: 8542320201
ECCN:: 3A991.b.2.b

SigmaQuad-II+ SRAMs

GSI Technology SigmaQuad-II+ SRAMs have built-in compliance with the SigmaQuad-II+ SRAM pinout standard for Separate I/O synchronous SRAMs. The SigmaQuad-II+ are 301,989,888-bit (288Mb) SRAMs. The SigmaQuad-II+ SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.

Quad SRAMs

GSI Technology Quad SRAMs combine capacity and performance with the ability to transfer four beats of data (two beats per data bus) in a single clock cycle. SigmaQuad SRAMs are synchronous memories with separate read and write data buses with unequaled transaction rates by competitors.