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LS2044ASN711B

Name: NXP LS2044ASN711B
Brand: NXP Semiconductors
SKU: 771-LS2044ASN711B
Price: 6494602.92 IDR
Availability: OutOfStock

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Mouser No:

771-LS2044ASN711B

Mfr. No:

LS2044ASN711B

Mfr.:

NXP Semiconductors

Description:

Microprocessors - MPU Layerscape 64-bit Arm Cortex-A72, Quad-core, 2.1GHz, 0 to 105C, Security disabled

ECAD Model:

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This product may require additional documentation to export from the United States.

Availability

Stock:: Non-Stocked

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Factory Lead Time:: 26 Weeks Estimated factory production time.

Long lead time reported on this product.

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Pricing (IDR)

Qty.	Unit Price	Ext. Price
	Rp6.494.602,92	Rp136.386.661,32

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	NXP
Product Category:	Microprocessors - MPU
Delivery Alerts:	This product may require additional documentation to export from the United States.
RoHS:
Core:	ARM Cortex A72
Number of Cores:	4 Core
Data Bus Width:	64 bit
Maximum Clock Frequency:	2.1 GHz
Package/Case:	FCPBGA-1292
L1 Cache Instruction Memory:	48 kB
L1 Cache Data Memory:	32 kB
Operating Supply Voltage:	1.05 V
Series:	LS2044A
Mounting Style:	SMD/SMT
Minimum Operating Temperature:	0 C
Maximum Operating Temperature:	+ 105 C
Packaging:	Tray
Brand:	NXP Semiconductors
Country of Assembly:	Not Available
Country of Diffusion:	Not Available
Country of Origin:	KR
Data RAM Size:	128 kB
Interface Type:	Ethernet, I2C, PCI-e, Serial, USB
L2 Cache Instruction / Data Memory:	2 x 1 MB
Memory Type:	DDR4 SDRAM
Moisture Sensitive:	Yes
Number of Timers/Counters:	4 Timer
Processor Series:	QorIQ LS2044A
Product Type:	Microprocessors - MPU
Factory Pack Quantity:	21
Subcategory:	Microprocessors - MPU
Tradename:	QorIQ
Watchdog Timers:	No Watchdog Timer
Part # Aliases:	935371379557

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CNHTS:: 8542319091
USHTS:: 8542310045
TARIC:: 8542319000
ECCN:: 3A991.a.1

Layerscape Architecture

NXP Layerscape Architecture is the underlying system architecture of the QorIQ® LS series processors. The architecture enables next-generation networks with up to 100Gb/s performance and enhanced packet processing capabilities. Design effort is simplified with a standard, open programming model and a software-aware architecture framework. This design enables customers to fully exploit the underlying hardware for maximum optimization, with the capability to easily adapt to network changes for real-time soft control over the network. A uniform hardware and software model provides the compatibility and scalability required for designing end-to-end networking equipment from home-to carrier-class products. The core-agnostic architecture incorporates the optimum core for the given application: Arm® cores or Power Architecture® cores.