SN74LVC166ADR

Texas Instruments
595-SN74LVC166ADR
SN74LVC166ADR

Mfr.:

Description:
Counter Shift Registers 1.1V to 3.6V 8-bit p arallel-load shift

Lifecycle:
New Product:
New from this manufacturer.
Datasheet:
ECAD Model:
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In Stock: 2.700

Stock:
2.700 Can Dispatch Immediately
Factory Lead Time:
18 Weeks Estimated factory production time for quantities greater than shown.
Minimum: 1   Multiples: 1
Unit Price:
Rp-
Ext. Price:
Rp-
Est. Tariff:
Packaging:
Full Reel (Order in multiples of 3000)

Pricing (IDR)

Qty. Unit Price
Ext. Price
Cut Tape / MouseReel™ †
Rp11.386 Rp11.386
Rp8.110 Rp81.100
Rp7.287 Rp182.175
Rp6.359 Rp635.900
Rp5.921 Rp1.480.250
Rp5.658 Rp2.829.000
Rp5.553 Rp5.553.000
Full Reel (Order in multiples of 3000)
Rp5.168 Rp15.504.000
Rp5.027 Rp30.162.000
† A MouseReel™ fee of Rp98.000 will be added and calculated in your basket. All MouseReel™ orders are non-cancellable and non-returnable. ↩

Product Attribute Attribute Value Select Attribute
Texas Instruments
Product Category: Counter Shift Registers
RoHS:  
Shift Register
Serial to Parallel
8 bit
SOIC-16
LVC
13 Input
Push-Pull
11.2 ns
1.1 V
3.6 V
- 40 C
+ 125 C
Reel
Cut Tape
MouseReel
Brand: Texas Instruments
Country of Assembly: MX
Country of Diffusion: US
Country of Origin: MX
Features: Back Drive Protection
High Level Output Current: - 24 mA
Input Type: Serial
Low Level Output Current: 24 mA
Mounting Style: SMD/SMT
Number of Output Lines: 1 Output
Operating Supply Voltage: 1.1 V to 3.6 V
Product: Shift Registers
Product Type: Counter Shift Registers
Series: SN74LVC166A
Factory Pack Quantity: 3000
Subcategory: Logic ICs
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Attributes selected: 0

Datasheet

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USHTS:
8542390090
TARIC:
8542319000
MXHTS:
8542399999
ECCN:
EAR99

SN74LVC166A 8-Bit Parallel-Load Shift Register

Texas Instruments SN74LVC166A 8-Bit Parallel-Load Shift Register contains one 8-bit parallel-load shift register. Data is loaded synchronously using the shift or load (SH/LD) select and clock (CLK) inputs. The Texas Instruments SN74LVC166A includes a serial (SER) input to allow for daisy chaining and an asynchronous clear (CLR) input.

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