SN74SSTUB32864NMJR

Texas Instruments
595-74SSTUB32864NMJR
SN74SSTUB32864NMJR

Mfr.:

Description:
Buffers & Line Drivers 410-MHz 25-bit conf igurable registered

Datasheet:
ECAD Model:
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Learn more about Texas Instruments SN74SSTUB32864NMJR

In Stock: 948

Stock:
948 Can Dispatch Immediately
Factory Lead Time:
6 Weeks Estimated factory production time for quantities greater than shown.
Quantities greater than 948 will be subject to minimum order requirements.
Minimum: 1   Multiples: 1
Unit Price:
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Ext. Price:
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Packaging:
Full Reel (Order in multiples of 1000)

Pricing (IDR)

Qty. Unit Price
Ext. Price
Cut Tape / MouseReel™ †
Rp256.273,71 Rp256.273,71
Rp194.613,87 Rp1.946.138,70
Rp186.556,05 Rp4.663.901,25
Rp164.484,63 Rp16.448.463,00
Rp156.426,81 Rp39.106.702,50
Rp146.266,95 Rp73.133.475,00
Full Reel (Order in multiples of 1000)
Rp135.931,92 Rp135.931.920,00
2.000 Quote
† A MouseReel™ fee of Rp98.000,00 will be added and calculated in your basket. All MouseReel™ orders are non-cancellable and non-returnable. ↩

Product Attribute Attribute Value Select Attribute
Texas Instruments
Product Category: Buffers & Line Drivers
RoHS:  
SSTUB
18 Input
18 Output
Non-Inverting
LFBGA-96
- 8 mA
8 mA
200 uA
1.7 V
1.9 V
40 mA
- 40 C
+ 85 C
SMD/SMT
Reel
Cut Tape
MouseReel
Brand: Texas Instruments
Country of Assembly: Not Available
Country of Diffusion: Not Available
Country of Origin: PH
Logic Type: Registered Buffer
Moisture Sensitive: Yes
Number of Channels: 25 Channel
Output Type: CMOS
Product Type: Buffers & Line Drivers
Propagation Delay Time: 1.6 ns
Series: SN74SSTUB32864
Factory Pack Quantity: 1000
Subcategory: Logic ICs
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Attributes selected: 0

Datasheet

PCN

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USHTS:
8542390090
TARIC:
8542399000
ECCN:
EAR99

SN74SSTUB32864 25-Bit Configurable Register Buffer

Texas Instruments SN74SSTUB32864 25-Bit Configurable Register Buffer is designed for 1.7V to 1.9V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive eighteen SDRAM loads. All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications.

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